This invention relates to quantum cascade semiconductor lasers, focusing in particular on thermal management and fabrication yield of such lasers.
Quantum cascade lasers (QCLs) are semiconductor lasers relying on intersubband transitions in quantum wells. They operate in continuous-wave (CW) mode at room temperature in the mid-infrared spectral range, i.e. at wavelengths of 3-50 μm.
Because QCLs operate at relatively large voltages of about 10 V and threshold current densities of the order of 1 kA/cm2, Joule heating in the gain region leads to a significant rise of internal temperature above heat-sink temperature during high-duty-cycle and CW operation. This self-heating generally results in performance degradation, as the laser efficiency decreases with increasing active region temperature. To keep this detrimental effect to a minimum, it is important to optimize heat transfer by using a heat-sink made of a high thermal conductivity material and by minimizing thermal resistance between the laser active region and said heat-sink.
The fabrication of QCLs, like most semiconductor lasers, starts by epitaxial growth of a semiconductor heterostructure on a substrate. The epitaxial side is then patterned to form a waveguide, an electrically insulating layer is deposited and selectively opened, and metallic layers are deposited for electrical contacting. An additional gold layer, typically 3-5 μm, is often electroplated on top of the contact layer to enhance heat dissipation by spreading heat laterally. The substrate side is thinned down to typically 100-200 μm and a metallic contact layer is deposited on it. For the device to emit light, current must flow between the epitaxial-side and the substrate-side contacts through the active region.
FIGS. 1a and 1b illustrate the two main classes of corresponding device geometries: FIG. 1a shows the first class, a ridge-waveguide (RWG) laser in which a thin layer of dielectric material, typically silicon nitride (Si3N4) or silicon oxide (SiO2), is used as insulator. The second class, a buried-heterostructure (BH) laser is shown in FIG. 1b, wherein a selective overgrowth of semi-insulating semiconductor material, typically iron-doped InP (Fe:InP), is used as insulator. The latter has the advantages of lower waveguide losses and higher thermal conductivity. FIGS. 1a and 1b are described in detail further down.
Of the buried heterostructure (BH) configurations mentioned above, at least two different types have been demonstrated for QCLs, which we will call here “standard BH” and “inverted BH”. In the standard BH, a planar top cladding is grown first, a ridge is then etched in the top cladding and active region, and finally semi-insulating material is selectively overgrown on the sides of said ridge to complete the waveguide.
FIG. 2 shows a so-called “inverted” BH QCL as described by A. Bismuto et al. in the yet unpublished European Patent Application 13 405 109.3, filed 13 Sep. 2013. In this structure, a ridge is etched in the active region 14 prior to growing the cladding, semi-insulating material 15 is then selectively overgrown on the sides of the active region 14, and finally a planar top cladding 16 is grown over the entire structure to complete the waveguide. A metallic top contact layer 13 on an optional insulating layer 12, together with a not shown contact layer on the back of the substrate 17, provides the electrical energy to the QCL.
This device is called an “inverted BH QCL” because the order of carrying out the top cladding growth and selective overgrowth is inverted compared to the standard BH process. This inverted BH architecture has the advantage of requiring a thinner selective overgrowth, typically about 2-3 μm, than the standard architecture, typically about 6-7 μm.
QCL chips can be mounted either epitaxial-side-up (“epi-up”) or epitaxial-side-down (“epi-down”). Both the RWG and BH configurations are well suited for epi-up bonding. The BH configuration, with its flat top surface, is also naturally well suited for epi-down bonding. In the case of the RWG configuration, the double-channel, or double-trench, geometry as described by J. S. Yu et al. in “High-power λ˜9.5 μm quantum-cascade lasers operating above room temperature in continuous-wave mode”, Applied Physics Letters 88, 091113 (2006), where the waveguide is defined by etching two narrow channels, as shown in FIG. 3, is typically used for epi-down bonding.
In the epi-up configuration, the substrate side is soldered onto a heat-sink made of a high-thermal-conductivity material, e.g. copper using an electrically conductive solder material, typically indium (In) or gold-tin (AuSn). This bonding process typically results in a high fabrication yield, because a thick layer of solder material can be used without risking to short-circuit the device. However, the resulting thermal resistance is large because the heat generated in the active region has to cross the whole thickness of the substrate (>100 μm), which typically has a much lower thermal conductivity (68 W/mK for InP) than the heat-sink (401 W/mK for Cu).
In the epi-down configuration, on the other hand, the active region is located only a few microns away from the heat-sink, resulting in a much lower thermal resistance. Nevertheless, even though this configuration is preferable from a thermal standpoint, it is not always chosen by QCL manufacturers because it is more challenging to implement and often results in a lower fabrication yield if no special precautions are taken. This is because the active region is very close to the heat-sink and therefore solder material may ooze out on the sides of the chip during the bonding process which readily short-circuits the device, rendering it unusable.
To minimize the probability of short-circuiting devices during the epi-down bonding process, solder thickness needs to be kept low, typically only a few microns. Therefore, solder material has to be placed on the heat-sink using a vacuum deposition process. While it helps avoiding short circuits, using a thin solder layer thickness increases requirements on surface planarity: the presence of micron-sized protrusions or of curvature due to mechanical strain can prevent solder from wetting the whole surface and, thus, results in a poor thermal contact between chip and heat-sink. A trade-off between these two effects, which are both detrimental to fabrication yield, has to be found.
Even with a thin vacuum-deposited solder layer, the risk of shorting devices during epi-down bonding is still present. Since the chip surface is flat and pressure needs to be applied during the process, molten solder tends to flow outwards, towards the sides of the chip and to ooze out. As the sides of the chip are not electrically insulated, a small accumulation of solder which comes into contact with the substrate above the active region is sufficient to create a short circuit.
Kim et al. describe in US 2013/0243020 A1, Epitaxial-side-down mounted high-power semiconductor lasers, a configuration for epi-down bonding of RWG semiconductor lasers. In this scheme, the laser ridge is free-standing and posts of approximately the same height as the ridge are located on the both sides to provide mechanical stability and flatness of the bond. The empty volume between the ridge and posts provides a relief area for excess solder.
While the approach described reduces the probability of shorting devices during the epi-down bonding process, it has the drawback of significantly reducing the contact area between the chip and a heatsink, particularly in comparison to the double-channel RWG and BH configurations. Indeed, only the typically 1-50 μm wide RWG and the posts, which are typically square with a length of 20-100 μm on a side and separated by free space of typically 100-1000 μm, get soldered onto the heatsink. This only represents a small fraction of the total chip area. Consequently, mechanical robustness of the bond, which is usually quantified by its die shear strength value, is significantly reduced, so is the heat transfer from the chip to the heatsink.
The present invention overcomes this disadvantage because the solder relief trench according to the invention typically represents less than 20% of the total chip area. The chip is thus soldered onto the heat-sink over more than 80% of its area, resulting in higher die shear strength. In addition, the larger contact area results in an improved thermal conductivity, particularly in the BH configuration in which lateral heat dissipation is significant.